I. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device for use as a memory cell in an erasable programmable read only memory (EPROM) which has a floating gate and a control gate.
II. Description of the Prior Art
In conventional EPROM memory cells, a structure of the type shown in FIG. 1 is known. In FIG. 1, reference numeral 1 denotes a monocrystalline silicon substrate; 2, a field insulating film; 3 and 4, n.sup.+ -type source and drain regions formed apart from each other in the surface region of substrate 1; 5, a gate insulating film; 6, a floating gate formed on top of gate insulating film 5; 7, an insulating film formed on top of floating gate 6; 8, a control gate formed on top of insulating film 7; 9, a source electrode; 10, a drain electrode; and 11, an insulating film.
Information is written in a memory cell having the construction shown in FIG. 1 in the following manner. When a high voltage of, for example, +20 V or more is applied to drain electrode 10 and control gate 8 at the same time, electrons flow from source region 3 to drain region 4 and can cause the impact ionization (avalanche) phenomenon near drain region 4. Some of the electrons of the electron-hole pairs generated here pass through gate insulating film 5 and are injected into floating gate 6, where they are trapped.
When information has been written to the cell, the threshold voltage V.sub.TH is increased because of the electrons trapped in floating gate 6, and even if a read voltage is applied to control gate 8, the memory cell will not go ON. On the other hand, when information has not been written to the cell, i.e., when no electrons are trapped in gate 6, the threshold voltage is low and the cell will easily go ON if a read voltage is applied to the control gate.
As a result, with this type of memory cell it is possible to determine whether information has been written to the cell or not. It is also possible to erase already written information with ultraviolet rays and rewrite new information after erasure.
At present in the field of semiconductor devices, progress in element micropatterning technology is eye-opening, the reduction of channel length are particularly notable in order to increase the switching speed. In the area of EPROMs also, this reduction of memory cell channel length is proceeding rapidly.
In EPROMs, however, a significant problem has arisen along with the reduction of channel length. As channel length decreases, the electric field created in the channel region by the voltage applied between the source and the drain becomes stronger. As a result, even when a comparatively low voltage (about +5 V) used for EPROM readout is applied to the drain and gate, the electrons flowing from the source region to the drain region are accelerated by the strong electric field in the channel region and are able to obtain enough energy to cause the above-mentioned impact ionization in the portion of the channel region near the drain. When information readout is performed in EPROMs whose channel length has been reduced for the purpose of high integration, electrons are also trapped in the floating gate electrodes of memory cells not containing any information, thus making those cells impossible to distinguish from those actually containing information. This phenomenon is usually referred to as unintentional writing. In a highly integrated memory cell having the structure shown in FIG. 1, the unintentional writing can be prevented only by reducing the source voltage. As the source voltage drops, however, the speed of information readout become very slow.